Method for forming fine pitch structures

ABSTRACT

A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels. The rows on different levels can crisscross one another. Selectively removing material from some of the rows can from openings to form, e.g., contact vias.

REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 13/794,084, entitled METHOD FOR FORMING FINE PITCH STRUCTURES, filed Mar. 11, 2013, which is a divisional of U.S. patent application Ser. No. 12/140,928, entitled METHOD FOR FORMING FINE PITCH STRUCTURES, filed Jun. 17, 2008.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to techniques for fabricating closely spaced structures, such as, for example, features in an integrated circuit.

2. Description of the Related Art

Techniques for forming closely spaced structures have many applications. For example, integrated circuits are continuously being reduced in size. The sizes of the constituent features that form the integrated circuits, e.g., electrical devices and interconnect lines, are also constantly being decreased to facilitate this size reduction.

The trend of decreasing feature size is evident, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), flash memory, static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically includes millions of identical circuit elements, known as memory cells. A memory cell typically consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that may store one bit (binary digit) of data. A bit may be written to a cell through the transistor and may be read by sensing charge in the capacitor. Some memory technologies employ elements that can act as both a storage device and a switch (e.g., dendritic memory employing silver-doped chalcogenide glass) and some nonvolatile memories do not require switches for each cell (e.g., magnetoresistive RAM) or incorporate switches into the memory element (e.g., EEPROM for flash memory).

In another example, flash memory typically includes millions of flash memory cells containing floating gate field effect transistors that may retain a charge. The presence or absence of a charge in the floating gate determines the logic state of the memory cell. A bit may be written to a cell by injecting charge to or removing charge from a cell. Flash memory cells may be connected in different architecture configurations, each with different schemes for reading bits. In a “NOR” architecture configuration, each memory cell is coupled to a bit line and may be read individually. In a “NAND” architecture configuration, memory cells are aligned in a “string” of cells, and an entire bit line is activated to access data in one of the string of cells.

In general, by decreasing the sizes of the electrical devices that constitute a memory cell and the sizes of the conducting lines that access the memory cells, the memory devices may be made smaller. Additionally, storage capacities may be increased by fitting more memory cells on a given area in the memory devices. The need for reductions in feature sizes, however, is more generally applicable to integrated circuits, including general purpose and specialty processors.

The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to pattern these features. Typically, photolithography involves passing light through a reticle and focusing the light onto a photochemically-active photoresist material. As a result, the ultimate resolution of lithography techniques is limited by factors such as optics and light or radiation wavelength.

In conjunction with radiation of a particular wavelength, photolithography utilizes photoresist compatible with that radiation. After being developed, the photoresist acts as a mask to transfer a pattern to an underlying material. The photoresist is sufficiently robust to withstand the development step without deforming and is also sufficiently robust to withstand an etch for transferring the mask pattern to an underlying material. As feature sizes decrease, however, the widths of the photoresist mask features also decrease, but typically without a corresponding decrease in the heights of these mask features. Due to the high aspect ratio of these mask features, it may be difficult to maintain the structural integrity of these thin mask features during the development and pattern transfer steps. Thus, the availability of sufficiently robust photoresist materials can limit the ability of photolithography to print features, as those features continue to decrease in size.

Accordingly, there is a continuing need for high resolution methods to pattern features.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood from the Detailed Description and from the appended drawings, which are meant to illustrate and not to limit the invention.

FIGS. 1A and 1B are schematic cross-sectional side and top plan views of a partially formed structure, in accordance with some embodiments of the invention.

FIGS. 2A and 2B are schematic cross-sectional side and top plan views of the partially formed structure of FIGS. 1A and 1B after forming an opening in a sacrificial layer, in accordance with some embodiments of the invention.

FIGS. 3A and 3B are schematic cross-sectional side and top plan views of the partially formed structure of FIGS. 2A and 2B after depositing a seed wall, in accordance with some embodiments of the invention.

FIGS. 4A and 4B are schematic cross-sectional side and top plan views of the partially formed structure of FIGS. 3A and 3B after defining openings for deposition inhibiting sidewalls, in accordance with some embodiments of the invention.

FIGS. 5A, 5B and 5C are schematic cross-sectional side and top plan views of the partially formed structure of FIGS. 4A and 4B after forming deposition inhibiting sidewalls and a deposition inhibiting cap layer, in accordance with some embodiments of the invention.

FIGS. 6A and 6B are schematic cross-sectional side and top plan views of the partially formed structure of FIGS. 5A and 5B after defining an opening exposing sacrificial material, in accordance with some embodiments of the invention.

FIG. 7 is a schematic, cross-sectional side view of the partially formed structure of FIGS. 6A and 6B after removing sacrificial material to form a mold having an open volume, in accordance with some embodiments of the invention.

FIG. 8 is a schematic perspective view of the partially formed structure of FIG. 7, in accordance with some embodiments of the invention.

FIGS. 9A and 9B are schematic cross-sectional side and top plan views of the partially formed structure of FIGS. 7 and 8 after selectively depositing alternating rows of material in the mold, in accordance with some embodiments of the invention.

FIGS. 10A, 10B and 10C are schematic cross-sectional side and top plan views of the partially formed structure of FIGS. 9A and 9B after selectively removing depositing inhibiting sidewalls, the depositing inhibiting cap layer and one of the alternating rows of material, in accordance with some embodiments of the invention.

FIG. 11 is a schematic perspective view of the partially formed structure of FIGS. 9A and 9B after forming another mold overlying the selectively deposited alternating rows and depositing a second set of alternating rows of material in the other mold, in accordance with some embodiments of the invention.

FIG. 12 is a schematic, cross-sectional side view of the partially formed structure of FIG. 11 after removing the sidewalls and cap layer of the other mold, in accordance with some embodiments of the invention.

FIGS. 13A and 13B are schematic cross-sectional side and top plan views of the partially formed structure of FIG. 12 after selectively removing exposed parts of one of the rows in each of the sets of alternating rows, in accordance with some embodiments of the invention.

DETAILED DESCRIPTION

Embodiments of the invention allow for the formation of exceptionally small features by selectively depositing material. A vertically extending surface, e.g., a sidewall, provides a template and a seed surface for the selective deposition of a first material. A second material is then selectively deposited on the first material. By alternating the deposition of two or more materials, alternating rows of the first and second materials, and optionally more materials, can be formed. One of the deposited materials is selectively removed. In embodiments where more than two materials are deposited, a plurality of materials can be removed. Advantageously, in some embodiments, the remaining rows of materials can form structures in a final product, thereby avoiding the costs and lower throughput associated with the multiple pattern formation and pattern transfer steps common to some integrated circuit fabrication processes. In some other embodiments, the free-standing rows can be used as hard masks for patterning an underlying substrate. In these applications, embodiments of the invention can avoid expensive and complicated lithography-based processes typically used to pattern small features.

It will be appreciated that deposition processes typically deposit material on all exposed surfaces. To selectively deposit on the seed surface, other exposed surfaces are formed of, or coated by, deposition inhibiting material. For example, in some embodiments, the seed surface is formed of a conductive material that facilitates electrochemical deposition on that surface, while other surfaces are formed of an insulating material that inhibits electrochemical deposition on those surfaces. As another example, in some other embodiments, the seed surface is formed of a material that allows chemical vapor deposition on that surface, while the other exposed surfaces include deposition inhibiting materials.

In some embodiments, the seed surface is provided in a mold having an opening. The ceiling, floor and sidewalls that define the interior volume of the mold having exposed deposition inhibiting surfaces. The seed surface forms an interior sidewall of the mold and the opening allows deposition precursors to enter the mold and deposit on the seed sidewall. The deposited material grows laterally, so that alternating rows of material also grow laterally within the mold. The height of the mold opening determines the height of the rows and the length of the rows is determined by the distance between opposing deposition inhibiting sidewalls at opposite ends of the rows. After the deposition of the rows of material, the mold can be selectively removed. In addition, desired rows of the deposited material can be removed to form free-standing, laterally-spaced rows formed of the remaining deposited material.

Advantageously, the deposition process controls the widths of the rows. In some embodiments, the deposition process can form rows that are thinner than rows that can be directly patterned by typical lithographic processes, such as 193 nm or 248 nm wavelength systems. Thus, sublithographic features can be formed. For example, features having a critical dimension in the range of about 1 nm to about 100 nm, or about 2 nm to about 50 nm, or about 3 nm to about 30 can be formed

Reference will now be made to the Figures, wherein like numerals refer to like parts throughout. It will be appreciated that the Figures are not necessarily drawn to scale.

In a first phase of methods according to some embodiments, a mold having a seed wall is formed. With reference to FIGS. 1A and 1B, cross-sectional side and top plan views of a partially formed structure 100 are illustrated. It will be appreciated that the partially formed structure 100 is a partially formed integrated circuit in some embodiments.

With continued reference to FIGS. 1A and 1B, a substrate 110 is overlaid by a bottom deposition inhibiting layer 120, which is overlaid by a layer 130 of sacrificial material. The layers 120, 130 can be deposited by various deposition processes known in the art, the processes selected depending on the identity of the material to be deposited. Examples of deposition processes include vapor deposition processes, such as chemical vapor deposition (CVD), and spin on deposition processes.

The substrate 110 can be various objects over which a pattern will be formed. The substrate 110 can include a single material, a plurality of layers of different materials, a layer or layers having regions of different materials or different structures in them, etc. In some embodiments, these materials can include semiconductors, insulators, conductors, or combinations thereof. For example, the substrate can comprise doped polysilicon, a single crystal electrical device active area, a silicide, or a metal layer, such as a tungsten, aluminum or copper layer, or combinations thereof. In some embodiments, the substrate 110 includes a silicon wafer.

The bottom deposition inhibiting layer 120 can be deposited over the substrate 110 as a separate material, or can be formed by reaction of the substrate 110 to form a deposition inhibiting surface. The bottom deposition inhibiting layer 120 is chosen based upon the material to be deposited on the seed surface, the deposition process used to deposit the material and processing compatibility with other materials utilized with the partially formed structure 100.

The sacrificial material forming the sacrificial layer 130 is selectively removable relative to other exposed materials in the partially fabricated structure 100. An etch is ““selective” to a material if the etch removes that material without removing a substantial amount of other material(s) exposed to the same etch. An example of a sacrificial material is, without limitation, molybdenum.

With reference to FIGS. 2A and 2B, the sacrificial layer 130 is etched to form a seed trench 140. The seed trench 140 is sized and shaped to accommodate a later-formed seed material, as discussed herein. It will be appreciated that the seed trench 140 can be formed by subjecting the sacrificial layer 130 to various pattern forming processes. For example, in some embodiments, a selectively definable layer (not shown) is provided over the layer 130. The selectively definable layer can be a photoresist layer. The photoresist layer is exposed to radiation through a reticle and then developed to leave a pattern including openings corresponding to the seed trench 140. The pattern in the photoresist layer is then transferred to the sacrificial layer 130 to form the seed trench 140.

With reference to FIGS. 3A and 3B, a seed material is formed in the seed trench 140. The seed material can be deposited into the trench, e.g., by chemical vapor deposition, to form a seed wall 150.

With reference to FIGS. 4A and 4B, sidewall trenches 160 a, 160 b are formed by various pattern forming processes known in the art. In some embodiments, a selectively definable layer (not shown), e.g., a photoresist layer, is provided over the layer 130. The photoresist layer is then exposed to radiation through a reticle and then developed to leave a pattern with openings corresponding to the sidewall trenches 160 a, 160 b. The pattern is transferred to the sacrificial layer 130 to form the sidewall trenches 160 a, 160 b.

The sidewall trenches 160 a, 160 b are subsequently filled with deposition inhibiting material to form deposition inhibiting sidewalls. The sidewall trenches 160 a, 160 b contact at least a portion of the seed wall 150 and partially partition off a mass or volume of sacrificial material 132 in the layer 130.

With reference to FIGS. 5A, 5B and 5C, a deposition-inhibiting cap layer 170 is formed over the sacrificial layer 130 and the seed wall 150. In the illustrated embodiment, the deposition inhibiting cap layer 170 is deposited directly on the sacrificial layer 130 and the seed wall 150. With reference to FIGS. 5B and 5C, the deposited deposition inhibiting material fills the trenches 160 a, 160 b (FIG. 4B) to form deposition inhibiting sidewalls 170 a, 170 b. It will be appreciated that FIG. 5B shows, in dotted lines, the locations of the sidewalls 170 a, 170 b underneath the layer 170 a.

With reference to FIGS. 6A and 6B, the deposition inhibiting cap layer 170 is etched to define an opening 180 that exposes the sacrificial material 132. The location of the opening 180 is chosen to facilitate later removal of the sacrificial layer 130 and also to facilitate later selective deposition of materials beneath the layer 170.

The opening 180 can be formed by various patterning forming and etching methods known in the art. For example, in some embodiments, a photoresist layer (not shown) is deposited over the deposition inhibiting cap layer 170. The photoresist layer is then patterned to form openings corresponding to the sidewall openings 180. The pattern is then transferred to the deposition inhibiting cap layer 170 to form the openings 180. The transfer can be accomplished using an anisotropic etch.

With reference to FIGS. 7 and 8, the sacrificial layer 130 is removed, leaving a cavity 180 a. The cavity 180 a is delimited by the deposition inhibiting layers 120, 170 (forming a floor and ceiling, respectively, of the cavity 180 a) and the deposition inhibiting sidewalls 170 a, 170 b, which together form a mold 172, with the cavity 180 a being an interior volume of the mold 172. The seed sidewall 150 is disposed at one end of the cavity 180 a.

With reference to FIGS. 9A and 9B, a plurality of alternating mask materials are formed. In the illustrated embodiments, two materials are deposited. A first masking material is deposited on the seed wall 150. The first masking material is chosen to preferentially deposit on the seed wall 150 relative to the deposition inhibiting layers 120, 170 and also relative to the deposition inhibiting sidewalls 170 a, 170 b. The deposited first masking material forms a first row 200. The deposition continues until the row 200 reaches a desired width 202. The width 202 is approximately equal to the desired critical dimension of a feature formed using the row 200, or to an open volume having a desired width, in embodiments where the row 200 is removed.

The first row 200 roughly tracks the contours of the seed wall 150. While the seed wall 150 is illustrated extending lengthwise in a straight line for ease of illustration and description, in other embodiments, the seed wall 150 can curve or some portions of the wall 150 can extend at an angle relative to other portions. In some embodiments, the path of the wall 150 corresponds to the shape of the desired path of interconnects in an integrated circuit.

With continued reference to FIGS. 9A and 9B, a second material is deposited on an exposed side of the first row 200. The second material is chosen to preferentially deposit on the second row relative to the deposition inhibiting layers 120, 170 and also relative to the deposition inhibiting sidewalls 170 a, 170 b. The deposition of the second material continues to form a second row 210 having a desired width 212. The width 212 is equal to the desired critical dimension of a feature formed using the second rows 210 or, where the second rows 210 are to be removed, the width 212 is equal to a desired spacing between the first rows 200.

The deposition of the first and second materials continues in alternating fashion to form a plurality of alternating first rows 200 of the first material and second rows 210 of the second material. The alternating depositions are continued until a desired number of rows 200, 210 are formed. The deposition can be accomplished by, e.g., electrochemical deposition, chemical vapor deposition, or atomic layer deposition, depending on the materials forming the seed wall 150 and the first and second masking materials of the rows 200, 210, respectively. Preferably, the lateral distance between the opening 180 and the seed wall 150 (FIGS. 6A and 6B) is sufficiently large to extend over all desired rows 200, 210.

The first and second materials for the first and second rows 200, 210 are chosen to be selectively removable relative to each other. The materials forming the deposition inhibiting cap layer 170 and the sidewalls 170 a, 170 b are also chosen to be selectively removable relative to the row of the rows 200, 210 that is to be retained. In the illustrated embodiment, the row 200 is to be retained and other exposed materials are selectively removable relative to that row 200.

With reference to FIGS. 10A and 10B, the deposition inhibiting cap layer 170 and the sidewalls 170 a, 170 b are selectively removed. The removal can be accomplished using a wet or dry etch. Subsequently, the second rows 210 are removed. Separated, free-standing layers 200 are left remaining over the bottom deposition inhibiting layer 170.

It will be appreciated that in some embodiments, the rows 200 can be used as mask features to allow a pattern transfer to an underlying material. For example, with reference to FIG. 10C, the rows 200 can be used to define a pattern in the bottom deposition inhibiting layer 120. The pattern transfer can be accomplished using an anisotropic etch selective for the bottom deposition inhibiting layer 120. In some embodiments, the pattern can be further transferred to the substrate 100. The pattern transfer can define various features in the partially formed structure 100, including, without limitation, interconnects for connecting electrical devices, preferably devices arranged in an array, such as the electrical devices which form a logic array or memory cells in the array region of a memory circuit. In some embodiments, substrate 100 includes a metal and the rows 200 directly define interconnects in the metal. In some other embodiments, the substrate 100 includes an insulator and the rows 200 define trenches that are later filled with metal to form interconnects.

In other embodiments, the rows 200 can be used as mandrels in a pitch multiplication process. Pitch multiplication is disclosed in U.S. Pat. No. 5,328,810 to Lowrey et al. and U.S. Pat. No. 7,253,118 to Tran et al. For example, a blanket layer of spacer material can be deposited on the rows 200. The blanket layer is anisotropically etched to define spacers on sidewalls of the rows 200. The rows 200 are selectively removed, thereby forming free-standing spacers. The free-standing spacers are used as masking features to define patterns in underlying materials. For example, the spacers can be used as mask features to etch an underlying substrate

In some other embodiments, the rows 200 can form a part of a final structure. For example, where the rows 200 are formed of a conductor, the rows 200 can be used as interconnects. Where the rows 200 are formed of an insulator, metal can be deposited in the spaces between the rows 200 to form conductive interconnects.

With reference to FIG. 11, multiple levels of selectively deposited rows can be formed. An underlying level of rows including the rows 200, 210 is formed as discussed above with reference to FIGS. 1A-9A. The deposition inhibiting cap layer 170 is retained and a new mold is formed overlying the layer 170, in a similar manner as discussed above with reference to FIGS. 1A-8.

FIG. 11 shows a cross-sectional perspective view in which one of the depositing inhibiting sidewalls on each level is not shown, to allow illustrate of the orientation of rows on each level. As illustrated, the new mold includes a seed sidewall 131, a deposition-inhibiting sidewall 173, a depositing-inhibiting cap layer 175 and the deposition inhibiting layer 170. In some embodiments, the materials forming the seed sidewall 131, the deposition-inhibiting sidewall 173, and the depositing-inhibiting cap layer 175 can be the same as that forming the seed sidewall 130, the deposition-inhibiting sidewall 170 a and the deposition inhibiting layer 170, respectively. The new mold is formed at a desired orientation relative to the underlying rows 200, 210. In some embodiments, the new mold is oriented to form alternating rows of different masking materials which crisscross the rows 200, 210.

With continued reference to FIG. 11, rows 204 formed of the first material are formed alternating with rows 214 formed of the second material.

With reference to FIG. 12, the rows 204 and 214 are exposed. The rows 204 and 214 are exposed by removing the sidewalls (including the illustrated sidewall 173 of FIG. 11) and the cap layer 175.

With reference to FIGS. 13A and 13B, exposed features formed of the second material are removed. A crisscrossing pattern of rows 200 and 204 is formed. The rows 200, 204 define open columns in the spaces between them. As noted herein, the crisscrossing pattern can be utilized as part of a final structure (e.g., crossing interconnects), or as a mask to form a pattern in underlying materials. The openings in the crisscrossing pattern can be filled to form isolated pillar shapes, including pillars having rectangular or cubic horizontal cross-sectional areas. Such an arrangement can be useful for forming, e.g., contact plugs. In addition, the pillars can advantageously be applied in some arrangements for patterning arrays of features, particularly dense arrays of features, such as capacitors for memory applications, including DRAM, or as memory elements for MRAM or STTRAM.

It will be appreciated that the various materials for the deposition inhibiting layers 120, 170, the deposition inhibiting sidewalls 170 a, 170 b, and the seed sidewall 150 are chosen based upon the materials that will be deposited in the cavity 180 a (FIG. 7), and based upon, e.g., etch and deposition compatibility with the other materials forming the partially formed structure 100. For example, in some embodiments, the bottom deposition inhibiting layer 120 is formed of an insulator and the seed wall 150 is formed of a conductor. The first and second materials are deposited by electrochemical deposition. In some embodiments, gold and silver are used as the first and second materials. In another example, gold and nickel are used. Plating solutions including the desired metal species can be introduced into the opening 180. In some embodiments, the plating solution contains both materials. The seed wall 150 can be connected to a power source and deposition occurs when current is flowed through the solution. In some embodiments, the seed wall 150 can be connected to a power source through the substrate 110. For example, the seed wall 150 can be made to extend through the deposition inhibiting layer 120 to contact the substrate 110, which may be formed of conductive or semiconductive material and which is connected to one of the electrodes of the power source. The width of each row can be controlled by selection of the charge passed during the deposition and by selection of the concentrations of the metal species. For example, to increase the width of a row formed by one of the metals, the concentration of that metal can be increased. Suitable selective deposition methods are discussed in Qin et al., Science, Vol. 309, Jul. 1, 2005, pp. 113-115.

Once deposited and after the rows 200, 210 are exposed, one of the metals can be removed by an appropriate etch. For example, Ni can be selectively removed relative to gold using a wet etch, such as a wet etch including concentrated HNO₃. In another example, where gold and silver are used the first and second materials, silver rows can be selectively removed using a wet etch formed of methanol, 30% ammonium hydroxide and 30% hydrogen peroxide (4:1:1 v/v/v). Suitable etch methods are discussed in Qin et al., Science, Vol. 309, Jul. 1, 2005, pp. 113-115.

In another example, materials are selectively deposited in the cavity 180 a by atomic layer deposition (ALD). In some embodiments, the seed sidewall 150 is formed of silicon, and the deposition inhibiting layers 120, 170, and the deposition inhibiting sidewalls 170 a, 170 b are formed of silicon oxide having a chemically modified surface. The deposition inhibiting layers 120, 170, and the deposition inhibiting sidewalls 170 a, 170 b are formed as described above, and then exposed to another chemical species to form a deposition inhibiting layer on exposed silicon oxide surfaces. For example, octadecyltrichlorosilane (ODTS) can be provided to the cavity 180 a, where it is selectively adsorbed on silicon oxide surfaces relative to the silicon seed sidewall 150. The ODTS forms a self-assembled monolayer (SAM) on the surfaces of the deposition inhibiting layers 120, 170, and the deposition inhibiting sidewalls 170 a, 170 b.

Next, the row 200 is formed by selective atomic layer deposition on the seed sidewall 150. For example, the row 200 can be formed of HfO₂ deposited using tetrakis(dimethylamido)hafnium(IV) (Hf[N(CH₃)₂]₄ and water. Suitable methods for forming deposition inhibiting surfaces and depositing HfO₂ are discussed in Chen, Applied Physics Letters 86, 191910 (2005).

The row 210 is subsequently selectively deposited by atomic layer deposition on the deposited row 200. For example, ruthenium (Ru) is deposited on the sidewall of the HfO₂ row 200 to form the row 210. Suitable methods for selectively depositing Ru are discussed in Park, Applied Physics Letters 86, 051903 (2005).

The deposition of the HfO₂ and the Ru are alternately repeated to form a desired number of rows 200, 210. Subsequently, the rows 200, 210 are exposed, as discussed herein, and one of the rows is removed by exposure to etchant, e.g., in a wet etch selective for the material of one of the rows 200, 210 relative to other exposed materials.

In some embodiments, the inside surfaces of the cavity 180 a are exposed to ODTS one or more times during the deposition of the rows 200, 210 to build up the ODTS layer on those inside surfaces.

Advantageously, atomic layer deposition allows the rows 200, 210 to be formed with high precision regarding the widths 202, 212, since the widths can be controlled by the number of deposition cycles performed, as known in the art. As a result, exceptionally uniform rows 200, 210 can be formed. In some other applications, the layer by layer deposition mechanism of ALD allows the formation, as desired, of rows 200, 210 having different widths.

In addition to forming integrated circuits, it will be appreciated that the selectively deposited rows disclosed herein can be used in various other applications where the formation of patterns with very small features is desired. For example, the preferred embodiments can be applied to form gratings, disk drives, storage media or templates or masks for other lithography techniques, including X-ray or imprint lithography. In other applications, multiple levels of the rows can be utilized in various light bending applications, in which spatially isolated blocks of material are formed “floating” and separated from other blocks of materials.

Floating blocks of material can be formed by depositing material into vias formed by crisscrossing rows of masking material (FIG. 13B) and the vias can be overlaid with material and additional vias can be formed and filled at a higher level. In other cases, the blocks of material can be the first or second masking materials themselves, with the molds dimensioned to form short blocks, rather than long rows of masking material. The deposition inhibiting material can be used to separate neighboring pluralities of the blocks.

It will be appreciated that only a section of the partially-formed structure 100 is shown. In some embodiments, a plurality of the molds 172 can be formed across the surface of the substrate 110 in a desired pattern. For example, the molds 172 can be formed in a regular array over the substrate 110 to pattern a regular array of features. For example, these features can be advantageously applied to form features in integrated circuit utilizing arrays of features, e.g., to form logic circuitry or memory devices, including flash memory or DRAM.

Also, while “processing” through a mask preferably involves etching underlying material(s), processing through the mask can involve subjecting material(s) underlying the mask materials to any semiconductor fabrication process. For example, processing can involve ion implantation, diffusion doping, depositing, oxidizing (particularly with use of a hard mask under the polymer mask), nitridizing, etc. through the mask layers and onto underlying layers. In addition, the mask can be used as a stop or barrier for chemical mechanical polishing (CMP) or CMP can be performed on various material(s) to allow for both planarization and etching.

It will be appreciated from the description herein that the invention includes various aspects. For example, according to one aspect of the invention, a patterning method is provided. The method comprises providing a substrate having a top surface that comprises a deposition inhibiting material. A mass of a sacrificial material is provided over the deposition inhibiting material. A seed wall is formed on one side of the mass of the sacrificial material. First and second deposition inhibiting walls are formed on opposite sides of the mass of the sacrificial material. The seed wall is disposed between and contacting the first and second deposition inhibiting walls. A deposition inhibiting cap layer is formed over the mass of the sacrificial material. The mass of the sacrificial material is selectively removed to form an open volume at least partially bounded by the seed wall, the first and second deposition inhibiting walls, the deposition inhibiting material and the cap layer. First and second materials are alternatingly deposited in the open volume.

According to another aspect of the invention, a method for forming a pattern is provided. The method comprises providing a substrate. A hollow mold is provided overlying the substrate. The mold has an opening into an open internal volume and a seed sidewall partially delimiting the open volume. A first material is selectively deposited on the seed sidewall in the open volume. A second material is selectively deposited on a side of the first material in the open volume.

According to yet another aspect of the invention, a method for depositing materials in a desired pattern is provided. The method comprises providing a substrate. The substrate is alternatingly exposed to first and second material precursors to deposit first and second materials on a first level. Depositing the first and second materials sequentially laterally grows a first plurality of alternating rows of the first and the second materials. One of the first and second materials is selectively removed relative to the other of the first and second materials.

In addition to the above disclosure, it will also be appreciated by those skilled in the art that various omissions, additions and modifications may be made to the methods and structures described above without departing from the scope of the invention. All such modifications and changes are intended to fall within the scope of the invention, as defined by the appended claims. 

We claim:
 1. A method for semiconductor processing, comprising: sequentially laterally growing a first plurality of alternating rows formed of first and the second materials on a first level over a substrate, wherein the rows alternate as seen in a top-down view; selectively removing the rows formed of the first material relative to the rows formed of the second material; and transferring a pattern formed by the rows of the second material to the substrate.
 2. The method of claim 1, wherein sequentially laterally growing comprises depositing an initial row formed of the first material before depositing an initial row formed of the second material.
 3. The method of claim 2, further comprising forming a wall on the substrate before sequentially laterally growing, wherein sequentially laterally growing comprises depositing the initial row formed of the first material directly on the wall.
 4. The method of claim 1, wherein transferring the pattern to the substrate comprises defining trenches in the substrate.
 5. The method of claim 4, wherein the trenches are disposed parallel to one another.
 6. The method of claim 4, wherein the substrate comprises an insulator and wherein the trenches are formed in the insulator, further comprising: filling the trenches with a metal.
 7. The method of claim 6, wherein filling the trenches forms electrical interconnects.
 8. The method of claim 1, further comprising sequentially laterally growing a second plurality of alternating rows of different materials on a second level over the first level, wherein the rows alternate as seen in a top-down view.
 9. The method of claim 8, wherein sequentially laterally growing the second plurality of alternating rows is performed before selectively removing the rows formed of the first material.
 10. The method of claim 9, further comprising depositing a deposition inhibiting layer over the first plurality of alternating rows before sequentially laterally growing the second plurality of alternating rows.
 11. The method of claim 10, further comprising: selectively removing one of the materials forming the second plurality of alternating rows, thereby forming a set of rows separated by openings, wherein the openings expose portions of the deposition inhibiting layer; selectively removing the exposed portions of the deposition inhibiting layer, thereby exposing portions of the first plurality of alternating rows; and selectively removing the exposed portions of the first plurality of alternating rows, thereby forming a plurality of vertically-elongated holes.
 12. A method for semiconductor processing, comprising: alternatingly depositing rows of a first material and rows of a second material on a level over a substrate; and selectively removing the rows of the first material relative to the rows of the second material.
 13. The method of claim 12, wherein alternatingly depositing comprises depositing an initial row of the first material before depositing an initial row of the second material.
 14. The method of claim 12, wherein alternatingly depositing comprises depositing rows of one or more additional materials in a sequence with depositing rows of the first and second materials.
 15. The method of claim 12, wherein alternatingly depositing comprises forming the rows of the first material by a vapor deposition process.
 16. The method of claim 15, wherein alternatingly depositing comprises forming the rows of the first material by atomic layer deposition.
 17. The method of claim 15, wherein alternatingly depositing comprises forming the rows of the second material by a vapor deposition process
 18. The method of claim 17, wherein alternatingly depositing comprises forming the rows of the second material by atomic layer deposition.
 19. A method for semiconductor processing, comprising: performing a plurality of cycles of row formation on a level over a substrate, each cycle comprising: depositing a row of a first material; and depositing a row of a second material; forming a etch mask by removing rows of the first material relative to rows of the second material, the rows of the first material forming the etch mask; and etching underlying material through the etch mask to define a pattern in the underlying material.
 20. The method of claim 19, wherein depositing the row of the first material is performed before depositing the row of the second material. 